Hamming codes are used for error detection and correction in communication and memory systems. Error detection and

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Hamming codes are used for error detection and correction in communication and memory systems. Error detection and correction capability is incorporated in these codes by inserting extra bits into the data word. Addition of one parity bit can detect odd number of bit flips, but no error correction is possible with one parity bit. A (7,4) Hamming code has 4 bits of data but 7 bits in total, including the 3 parity bits. It can detect two errors and correct one error. This code can be constructed as follows: If we denote data bits as d4d3d2d1, the encoded code word would be d4d3d2p4d1p2p1, where p4, p2, and p1 are the added parity bits. These bits must satisfy the following conditions for even parity:

p4 = d2 XOR d3 XOR d4;……………………….(1)
p2 = d1 XOR d3 XOR d4;……………………….(2)
p1 = d1 XOR d2 XOR d4;……………………….(3)
When the 7 bits are received/decoded, an error syndrome S3S2S1 is calculated as follows:
p4 XOR d2 XOR d3 XOR d4 = S3;……………………….(4)
p2 XOR d1 XOR d3 XOR d4 = S2;……………………….(5)
p1 XOR d1 XOR d2 XOR d4 = S1;……………………….(6)
The syndrome indicates which bit is wrong. For example, if the syndrome is 110, it indicates that bit 6 from right end (i.e., d3) has flipped. If S3S2S1 is 000, there is no error. 

(a) Is there any error in the code word 0110111? If yes, which bit? What was the original data? What must be the corrected code word?
(b) How will these 6 equations get modified for odd parity? Write the 6 equations for odd parity.
(c) Write a Verilog module for error detection without using tasks. The inputs to the module are the 7-bit encoded data word and the type of parity, and the output is the syndrome. The type of parity is encoded as 0 for odd parity and 1 for even parity.

module error_detector(data, PARITY, Syndrome)
 {
 }

(d) Modify the Verilog module in (c) to use Verilog tasks. Write required Verilog task(s) that will generate the error syndrome given the code word. The input to the task is data, and output is the syndrome. You have to call necessary task(s) for each type of parity.
task error_p(data, Syndrome)
 {
 }

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Related Book For  answer-question

Digital Systems Design Using Verilog

ISBN: 978-1285051079

1st edition

Authors: Charles Roth, Lizy K. John, Byeong Kil Lee

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