Implement the following Verilog code using these components: D flip-flops with clock enable, a multiplexer, an adder, and any necessary gates. Assume that Ad and Ora will never be 1 at the same time and enable the flip-flops only when Ad or Ora is 1.
module module1(A,B,Ad,Ora,clk,C);
input Ad,Ora,clk;
input [2:0]A,B;
output reg[2:0]C;
initial
begin
C = 3'd0;
end
always @(posedge clk)
begin
if(Ad == 1'b1)
C <= A + B;
if(Ora == 1'b1)
C <= A | B;
end
endmodule