For the following Verilog code, assume that D changes to 1 at time 5 ns. Give the values of A, B, C, D, E, and F each time a change occurs. That is, give the values at time 5 ns, 5 + D, 5 + 2D, and so forth. Carry this out until 20 steps have occurred, until no further change occurs, or until a repetitive pattern emerges.

module prob(D);
inout D;
wire A, C;
reg B,E,F,temp_D;
initial begin
B = 1'b0;
E = 1'b0;
F = 1'b0;
temp_D = 1'b0;
end

assign C = A;
assign A = (B & !E) | D;
assign D = temp_D;
always @(A)
begin
B = A;
end
always  

begin
wait(A)
E <= #5 B;
temp_D <= 1'b0;
F <= E;
end
endmodule