Consider the situation of Figure 5-67 for each of the following sets of timing values. For each,

Question:

Consider the situation of Figure 5-67 for each of the following sets of timing values. For each, indicate whether or not flip-flop Q2 will respond correctly.

(a)* Each FF: TPLH = 12 ns; tpHL = 8 ns; ts = 5 ns; th 8 ns; tpHL 6ns 5ns (b) NAND gate: tpLH (c) INVERTER:


Figure 5-67

CLOCK 1 +5 V D O CLK total delay = 1 (a) CLOCK 2 D CLK QCLOCK 1 CLOCK 2 Q 65 15 5 13 = = assume X HIGH skew 13 skew = combined delay of NAND gate and INVERTER IPLH

Fantastic news! We've Found the answer you've been seeking!

Step by Step Answer:

Related Book For  book-img-for-question

Digital Systems Principles And Application

ISBN: 9780134220130

12th Edition

Authors: Ronald Tocci, Neal Widmer, Gregory Moss

Question Posted: