Design a frequency divider circuit that will output either of two specified frequency signals. The output frequency is selected by the control input fselect. The divider will output a frequency of 5 kHz when fselect = 0 or 12 kHz when fselect = 1. The input frequency is 60 kHz.

Simulate (functional) the counter.

(a) Use LPM_COUNTER. Create a down counter that reloads the appropriate value (determined by fselect) after the terminal state is reached. You will also need one logic gate.

(b) Use an HDL.