Figure 5-65 shows a three-bit shift register made up of TTL flip-flops. Initially, all of the FFs are in the LOW state before clock pulses are applied. As clock pulses are applied, each PGT will cause the information to shift from each FF to the one on its right. The diagram shows the “expected” sequence of FF states after each clock pulse. Since J₂ = 1 and K₂ = 0, flipflop X₂ will go HIGH on clock pulse 1 and will stay there for all subsequent pulses. This HIGH will shift into X₁, and then X₀ on clock pulses 2 and 3, respectively. Thus, after the third pulse, all FFs will be HIGH and should remain there as pulses are continually applied.

Now let’s suppose that the “actual” response of the FF states is as shown in the diagram. Here the FFs change as expected for the first three clock pulses. From then on, flip-flop X₀, instead of staying HIGH, alternates between HIGH and LOW. What possible circuit fault can produce this operation?

Figure 5-65

Transcribed Image Text:

CLOCK n +5 V ول 012345678 CLK K₂ Clock pulse number NT X₂ O "Expected" X₂ X₁ Xo TT- ******** TTTTTTT J₁ O CLK K₁ 1 "Actual" X₂ X₁ X₂ 0 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1 1 X₁ 1 1 X₁ 1 1 1 1 1 1 0 Jo CLK Ko Xo Xo