Figure 7-73 shows an eight-bit shift register that could be used to delay a signal by 1 to 8 clock periods. Show how to wire a 74151 to this shift register in order to select the desired Q output and indicate the logic level necessary on the select inputs to provide a delay of 6 × T_clk.

Figure 7-73

Transcribed Image Text:

A B CP MR D rCDCP Q CLR Qo ID ODCP Q CLR Q₁ D Q CP CLR MR ♂ Eight-bit shit register 74ALS164 D >CP 20₁ CLR (a) Q 74ALS164 (b) D PODCP Q₂ Q CLR Q5 Qe Q7 P. D CDCP Q CLR Qs Q D ODCP CLR D ODCP CLR Q₂ Q7