Question: Modify (a) The AHDL design in Figure 4-63 to implement Table 4-1. (b) The VHDL design in Figure 4-64 to implement Table 4-1. Figure 4-63
Modify
(a) The AHDL design in Figure 4-63 to implement Table 4-1.
(b) The VHDL design in Figure 4-64 to implement Table 4-1.
Figure 4-63
![SUBDESIGN Figure 4-63 ( ) P, q, r S VARIABLE status [2..0] BEGIN END CASE; : INPUT; :OUTPUT; END; :NODE;](https://dsd5zvtm8ll6.cloudfront.net/images/question_images/1699/6/8/7/564654f2c8c0ec641699687563891.jpg)
Table 4-1
SUBDESIGN Figure 4-63 ( ) P, q, r S VARIABLE status [2..0] BEGIN END CASE; : INPUT; :OUTPUT; END; :NODE; status] (p, q, r); -- link input bits in order. CASE status [] IS WHEN b"100" WHEN b"101" WHEN b"110" WHEN OTHERS -- define inputs to block -- define outputs -> 3 - GND; ->s - GND; -> S GND; ->3- VCC;
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