Refer to Figure 10-43. The sub-blocks (encoder, divide-by counter, non-recycling counter, MUX) could be implemented as separate blocks in the third level of hierarchy of this project. Code can be found in previous examples that will work for each of these blocks with only slight modification. These functional elements can also be combined in a single HDL source file. Write the code for the entire encoder/timer control block in:

(a) AHDL 

(b) VHDL

Figure 10-43

Transcribed Image Text:

keypad 9..0] enablen 100 Hz clock Priority encoder Enablen BCD out Data valid Divide by 100 (4 Encoder Debounce delay Clear Non-recycling counter 0-7 >Clock 1 Hz Select MUX 1 1 D[3..0] loadn pgt 1Hz