Simulate the HDL design for a NAND latch given in Figure 5-76 (AHDL) or Figure 5-77 (VHDL). What does this S-R latch do if an “invalid” input command is applied? Since we know that any S-R latch can have an unusual output result when an invalid input command is applied, you should simulate that input condition as well as the latch’s normal set, reset, and hold commands. Some latch designs can have a tendency for the output to oscillate when an invalid command is followed by a hold command, so be sure to check for that in your simulation.

Figure 5-76

Figure 5-77

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SUBDESIGN fig5_76 sbar, rbar 9 ( ) BEGIN END; IF sbar 0 ELSIF rbar -- 0 ELSE END IF; :INPUT; :OUTPUT; THEN q vcc; THEN q- GND; q-q; set or illegal command reset hold