When the combination lock of Figure 5-103 is tested, it is found that entering the correct combination does not open the lock. A logic probe check shows that entering the correct first combination sets Q₁ HIGH, but entering the correct second combination produces only a momentary pulse at Q₂. Consider each of the following faults and indicate which one(s) could produce the observed operation. Explain each choice.

(a) Switch bounce at SWA, SWB, or SWC.

(b) CLR input of Q₂ is open.

(c) Connection from NAND gate 4 output to NAND gate 3 input is open.

Figure 5-103

Transcribed Image Text:

SWA SWB SWC +Vcc ww 5 6 ENTER O NO ONC N 7 +Voc +Vcc CLK D CLR CLR CLK Q₁ Q₂ +Vcc RESET OPEN LOCK