If both JFETs in the cascade amplifier of Fig. 8.93 are changed to those having specifications I
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If both JFETs in the cascade amplifier of Fig. 8.93 are changed to those having specifications IDSS = 12 mA and VP = -3 V, calculate the resulting dc bias of each stage.
Fig. 8.93
Transcribed Image Text:
+18 V 2.2 k2 2.2 k2 0.05 µF 0.1 µF 0.05 µF V 20 mV 10 M2 10 MQ 390 2 50 uF 390 2 50 µF FIG. 8.93
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Related Book For
Electronic Devices And Circuit Theory
ISBN: 9781292025636
11th Edition
Authors: Robert Boylestad, Louis Nashelsky
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