Repeat Problem 5.28 for the Verilog code in Figure P5.10.

Data From Problem 28

The Verilog code in Figure P5.9 represents a 3-bit linear-feedback shift register (LFSR).
This type of circuit generates a counting sequence of pseudo random numbers that repeats after 2ⁿ − 1 clock cycles, where n is the number of flip-flops in the LFSR. Synthesize a circuit to implement the LFSR in a chip. Draw a diagram of the circuit. Simulate the circuit’s behavior by loading the pattern 001 into the LFSR and then enabling the register to count. What is the counting sequence?

Transcribed Image Text:

module Ifsr (R, L, Clock, Q); input [0:2] R; input L, Clock; output reg [0:2] Q: always @(posedge Clock) if (L) Q<= R; else Q<= {Q[2], Q[0], Q[1] ^ Q[2]}; endmodule