A logic circuit is needed to implement the priority network shown in Figure 4.86. The network handles three interrupt request lines. When a request is received on line INTRI, the network generates an acknowledgment on line INTAI. If more than one request is received, only the highest-priority request is acknowledged, where the ordering of priorities is priority of INTR1 > priority of INTR2 > priority of INTR3

(a) Give a truth table for each of the outputs INTA1, INTA2, and INTA3.

(b) Give a logic circuit for implementing this priority network.

(c) Can your design be easily extended for more interrupt-request lines?

(d) By adding inputs DECIDE and RESET, modify your design such that INTAI is set to 1 when a pulse is received on the input DECIDE and is reset to 0 when a pulse is received on the input RESET.