A rate-1/3 convolutional encoder Consider a convolutional encoder for a K4 shift register with v3 modulo-2 adders. At each clock time the outputs of the

A rate-1/3 convolutional encoder Consider a convolutional encoder for a K¼4 shift register with v¼3 modulo-2 adders. At each clock time the outputs of the v adders are sampled by a commutator.

Thus v output symbols (v1,v2 ,v3) are generated for each input symbol, giving a code of rate 1/v. The equations for these three adders are v1 ¼ S1;

v2 ¼ S1 S2 S3 S4;

v3 ¼ S1 S3 S4:

Assuming that all shift registers are initially at zero, determine the first 18 output bits in the convolutional code for the message 110011. (Thus with 1 as the first bit, we have S1¼1, S2¼S3¼S4¼0).