The forwarding path in Figure 6.5 allows the contents of register RZ to be used directly in an ALU operation. The result of that operation is stored in register RZ, replacing its previous contents. This problem involves tracing the contents of register RZ over multiple cycles. Consider the two instructions

I ₁ : Add R3, R2, RI

1 ₂ : L Shift L R3, R3, #1

While instruction 11 is being fetched in cycle 1, a previously fetched instruction is performing an ALU operation that gives a result of 17. Then, while instruction 11 is being decoded in cycle 2, another previously fetched instruction is performing an ALU operation that gives a result of 198. Also during cycle 2, registers R1, R2, and R3 contain the values 30, 100, and 45, respectively. Using this information, draw a timing diagram that shows the contents of register RZ during cycles 2 to 5.

Transcribed Image Text:

RA MuxA A InA Figure 6.5 Register file ALU Out RZ 0 B RB 1 MuxB InB Immediate value 2 Modification of the datapath of Figure 5.8 to support data forwarding from register RZ to the ALU inputs. RA MuxA A InA Figure 6.5 Register file ALU Out RZ 0 B RB 1 MuxB InB Immediate value 2 Modification of the datapath of Figure 5.8 to support data forwarding from register RZ to the ALU inputs.

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