$10-38.$ U$5$ and U$6$ are octal $D$ flip$-$flops in the Watchdog Timer schematic. They provide two stages of latching for the $8-$bit data bus labeled $D(7$;$0).$

$($a$)$ How are they initially Reset? $($Hint: CLR is the abbreviation for CLEAR, which is the same as Master Reset.$)$

$($b$)$ What has to happen for the $Q-$outputs of U$5$ to receive the value of the data bus?

$($c$)$ What has to happen for the $Q-$outputs of U$6$ to receive the value of the U$5$ outputs?