$(10$ points$)$ Consider the execution of the following sequence of four instructions on a five$-$stage

pipelined processor which uses the always$-$not$-$taken strategy for branch prediction and has both

the forwarding unit and hazard detection unit.

add $x12,x6,x5$

sub $x10,x11,x12$

beq $x11,x12,$ LABEL

$sdx11,0(x12)$

Suppose the third instruction is detected to have an invalid target address and cause an exception

in the ID stage. Fill in the following table by showing what instructions are in the IF$,$ ID$,$ EX$,$

MEM and WB stages. Note that each instruction in your answer should be one chosen from the

given four instructions, the NOP instruction $($or bubble$),$ and the first instruction of the exception

handler.