1. 12 pts] Use a VHDL when or with-select statement to implement a 4-to-1 mux. Assume a 4-bit input bus "T" and a 2-bi select bus "S" are used as the inputs and "Y" is the output signal. 2. 1 pt] Suppose an enable input is added to the 4-to-1 mux from prelab problem 1. The enable input operates in the following manner: if enables 1, then the mux will operate normally, otherwise, if enable '0', then the output Y will be '0'. How must you change your VHDL code in order to correctly add and implement this enable signal? Please explain (you do not need to write the new VHDL code). Hint: You may want to revisit the lecture slides on std_logic_vectors to see how you can manipulate bits