Question: 1 ( 2 0 points ) Consider three different processors P 1 , P 2 , and P 3 executing the same instruction set. P
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Consider three different processors P P and P executing the same instruction set. P has a GHz clock
rate and a CPI of P has a GHz clock rate and a CPI of P has a GHz clock rate and has a CPI
of
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Calculate the performance of each processor expressed in instructions per second.
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If each of these processors executes a program in seconds, calculate the number of cycles and the number of
instructions.
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We are trying to reduce the execution time of P by but this leads to an increase of in the CPI. What
should the clock rate be to obtain this reduction in execution time?
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Consider two different implementations of the same instruction set architecture. The instructions can be divided
into four classes according to their CPI classes A B C and D P with a clock rate of GHz and CPIs of
and for the corresponding classes, and P with a clock rate of GHz and CPIs of and Given
a program with a dynamic instruction count of e instructions divided into classes as follows: class A
class B class C and class D:
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What is the total CPI for each implementation?
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Calculate the clock cycles required in both cases.
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Which is faster: P or P
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In this exercise we look at memory locality properties of matrix computation. The following code is written in
C where elements within the same row of a matrix are stored contiguously. You can assume that undefined
symbols are primitive types, ie int, double etc.
for int j ; j n; j
forint i ; i m; i
AnewjiAji Aji Aji Aji;
err maxerr fabsAnewji Aji;
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Which variables exhibit temporal locality?
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Which variables exhibit spatial locality? Locality is affected by both the reference order and data layout.
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Would the program be slower or faster if the outer loop iterated over i and the inner loop iterated over j Why?
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Consider a byte addressing architecture with bit memory addresses.
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Which bits of the address would be used in the tag, index and offset in a directmapped cache with word
blocks?
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Which bits of the address would be used in the tag, index and offset in a directmapped cache with word
blocks?
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What is the ratio of bits used for storing data to total bits stored in the cache in each of the above cases?
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Which bits of the address would be used in the tag, index and offset in a twoway set associative cache with
word blocks and a total capacity of words.
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