Consider the usage of critical word first and early restart on

L$2$ cache misses. Assume a $1$ MB L$2$ cache with $64-$byte blocks and a refill path

that is $16$ bytes wide. Assume that the L$2$ can be written with $16$ bytes every $4$

processor cycles, the time to receive the first $16$ byte block from the memory con$-$

troller is $120$ cycles, each additional $16$ byte block from main memory requires $16$

cycles, and data can be bypassed directly into the read port of the L$2$ cache. Ignore

any cycles to transfer the miss request to the L $2$ cache and the requested data to the

L$1$ cache.

a How many cycles would it take to service an L$2$ cache miss with

and without critical word first and early restart?

b Do you think critical word first and early restart would be more

important for L$1$ caches or L$2$ caches, and what factors would contribute to their

relative importance?