3. (a) A machine has 256K bytes of cache memory, and the cache block size is...

 

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3. (a) A machine has 256K bytes of cache memory, and the cache block size is 64 bytes. Two-way set associative cache organization is used. (1K=1024) (i) How many blocks are there in the cache memory? [2] (ii) Write down the number of sets in the cache memory. [2] (iii) Write down the number of bits in each field for the following 32-bit byte address. [2] Cache tag Cache Set Number Offset in the block (b) Consider a hypothetical machine with 1024 words of cache memory. They are in two-way set associative organization, with cache block size of 64 words, using LRU replacement algorithm. The cache hit time is 10ns. Suppose the machine can access 4 words of memory in parallel, and the time to transfer the first 4 words from main memory to cache is 55ns, while each subsequent 2 words require 10ns. Consider the following read pattern (in blocks of 64 words, and block id starts from 0): 0 1 2 4 5 2 3 9 4 7 10 0 8 3 7 1 7 10 7 12 14 6 5 8 10 11 9 20 12 17 14 23 and assume each block contains an average of 18 memory references. (i) What is the cache miss penalty (i.e., time to transfer one block of data from main memory to cache memory)? [2] (ii) Write down the contents of the cache memory (for all blocks) at the end of the memory references, assuming that the cache is empty at the begin- ning. [5] (iii) Write down the number of cache misses (the first reading of a block is also considered a miss), and the cache hit rate. [3] (iv) Calculate the average memory access time. [2] 3. (a) A machine has 256K bytes of cache memory, and the cache block size is 64 bytes. Two-way set associative cache organization is used. (1K=1024) (i) How many blocks are there in the cache memory? [2] (ii) Write down the number of sets in the cache memory. [2] (iii) Write down the number of bits in each field for the following 32-bit byte address. [2] Cache tag Cache Set Number Offset in the block (b) Consider a hypothetical machine with 1024 words of cache memory. They are in two-way set associative organization, with cache block size of 64 words, using LRU replacement algorithm. The cache hit time is 10ns. Suppose the machine can access 4 words of memory in parallel, and the time to transfer the first 4 words from main memory to cache is 55ns, while each subsequent 2 words require 10ns. Consider the following read pattern (in blocks of 64 words, and block id starts from 0): 0 1 2 4 5 2 3 9 4 7 10 0 8 3 7 1 7 10 7 12 14 6 5 8 10 11 9 20 12 17 14 23 and assume each block contains an average of 18 memory references. (i) What is the cache miss penalty (i.e., time to transfer one block of data from main memory to cache memory)? [2] (ii) Write down the contents of the cache memory (for all blocks) at the end of the memory references, assuming that the cache is empty at the begin- ning. [5] (iii) Write down the number of cache misses (the first reading of a block is also considered a miss), and the cache hit rate. [3] (iv) Calculate the average memory access time. [2]

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Sure lets tackle this step by step 1 a i The number of blocks in the cache memory can be calculated ... View the full answer