$12\mathrm{.}1\mathrm{.}5$ Design a Verilog model for an $8-$bit Ripple

Carry Adder $($RCA$)$ using a structural design

approach. This involves creating a half adder

$($half$\_$adder.v$),$ full adder $($full$\_$adder.v$),$ and

then finally a top$-$level adder $($rca$.$v$)$ by

instantiating eight full adder sub$-$systems.

Model the logic operations using gate level

primitives. Give each gate primitive a delay of

$1ns.$ The general topology and module defini$-$

tion for the design are shown in Fig. $12\mathrm{.}4.$ Cre$-$

ate a test bench to exhaustively verify your

design under all input conditions. The test

bench should drive in different values every

$30ns$ in order to give sufficient time for the

results to ripple through the adder.

Fig. $12\mathrm{.}4$

$4-$Bit RCA Module DefinitionDesign a Verilog model for an $8-$bit Ripple Carry Adder $($RCA$)$ using a structural design approach. This involves creating a half adder $($half$\_$adder.v$),$ full adder $($full$\_$adder.v$),$ and

then finally a top$-$level adder $($rca$.$v$)$ by instantiating eight full adder sub$-$systems. Model the logic operations using gate level primitives. Give each gate primitive a delay of

$1$ ns$.$ The general topology and module definition for the design are shown in the textbook Fig. $12\mathrm{.}4($page $400).$ Create a test bench to exhaustively verify your design under all input conditions. The test bench should drive in different values every $30$ ns in order to give sufficient time for the results to ripple through the adder.