$12.$ Consider a $1$Gbit DRAM integrated circuit organized as $128$ M addresses with one$-$byte words. The DRAM cells are arranged in a $16$ k by $64$ k grid $(16$ k rows and $64$ k columns$),$ each word occupies $8-$bits of a row, and the row number and column number concatenate to form the memory address.

$-$ What size address bus $($how many address lines$)$ is needed for the DRAM integrated circuit?

$-$ What size data bus $($how many data lines$)$ is needed for the DRAM integrated circuit?

$-$ How many words are stored in each row of the DRAM cell grid?

$-$ What size row decoder is required to select one row of the DRAM cell grid?

$-$ What size column decoder is required to select one of the words in a row of the DRAM cell grid?

$13.$ Consider constructing a $2$Gbyte memory system organized as $256$ M addresses with $8$ byte words using as many of the $1$Gbit DRAM integrated circuits of Problem $12$ as necessary.

$-$ What size address bus $($how many address lines$)$ is needed for the memory system?

$-$ What size data bus $($how many data lines$)$ is needed for the memory system?

$-$ How many of the $1$Gbit DRAM integrated circuits would be required for the memory system?

$-$ How many integrated circuits are needed in a bank to create the $8$byte word size?

$-$ How many banks are needed for the memory system?

$-$ What size external decoder is needed to select one of the banks in the memory system?