$14\mathrm{.}43($a$)$ Derive the state graph and table for a Mealy sequential circuit that converts a serial stream of bits from Manchester code to NRZ code. Assume that a double frequency clock $($Clock$2)$ is available.

$($b$)$ Repeat $($a$)$ for a Moore sequential circuit.

$($c$)$ Draw a timing diagram similar to Figure $14-20($b$)$ for your answer to $($a$),$ using the Manchester waveform in Figure $14-20($b$)$ as the input waveform to your circuit. If the input changes occur slightly after the clock edge, indicate places in the output waveform where glitches $($false outputs$)$ can occur. If possible, assign the don't$-$cares in the output part of your state table to eliminate some of the glitches.

$($d$)$ Draw the timing diagram for your answer to $($b$),$ using the same input waveform as in $($c$).$