$14.$ a$)(5)$ An instruction that immediately follows a load instruction is said to occupy a load delay slot. If the instruction in the load delay slot depends on the value read from memory by the load instruction, must the dependent instruction always be stalled? If so$,$ in which pipeline stage must the dependent instruction be stalled and for how many cycles? Explain your answer.

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b$)(3)$ Can a MIPS instruction cause a data hazard by writing its result to register $$0?$ Explain your answer.

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c$)(3)$ With our MIPS pipeline, what is the advantage of writing CPU registers in the first half of the clock cycle and reading CPU registers in the second half of the clock cycle? Explain your answer.