$1.<5\mathrm{.}0$ pts$>$ Given: $256$KB cache, $4-$way set associative, $64$ bytes$/$block and a $32-$bit total address space.

$1.$a$.(0\mathrm{.}5$ pts$)$ Given its size, how many bits of address space would be required to directly access each byte in the cache if it were like regular memory?

$1.$b$.(0\mathrm{.}5$ pts$)$ How many blocks are in this cache?

$1.$c$.(0\mathrm{.}5$ pts$)$ How many bits needed to access the block offset?

$1.$d$.(0\mathrm{.}5$ pts$)$ How many bits are used for the index?

$1.$e$.(0\mathrm{.}5$ pts$)$ How many bits are used for the tag?

$1.$f$.(0\mathrm{.}5$ pts$)$ How many sets $($i$.$e$.$ rows$)$ given this cache configuration and size?

$1.$g$.(0\mathrm{.}5$ pts$)$ How many different tags are possible?

$1.$h$.(0\mathrm{.}5$ pts$)$ Valid bits require additional physical cache memory since they must be stored in the cache. This is called overhead. How many BYTES of storage are required to store all the valid bits?

$1.$i$.(0\mathrm{.}5$ pts$)$ Tag bits also require additional physical cache memory since they must be stored in the cache. How many BYTES of storage are required to store all the tag bits?

$1.$j$.(0\mathrm{.}5$ pts$)$ What is the total amount of memory required to implement this cache?