Question: [ 1 5 1 5 ? ? 1 5 1 5 ? ? 2 5 1 0 ? 1 5 ] A . 2 >

[1515??1515??2510?15] A.2> Use the following code fragment:
Loop: 1dx1,0(x2) ;10adx1 from address 0+x2
addi x1,x1,1,;x1=x1+1
sdx1,0,(x2) store x1at address 0+x2
addi x2,2,4,;x2=x2+4
sub x4,x3,x2,;x4=x3-x2
bnez x4, Loop ;branch to Loop ifx40
Assume that the initial value of x 3 is x2+396.
d.[15] C.2> Show the timing of this instruction sequence for the 5-stage RISC pipeline with full forwarding and bypassing hardware, as shown in Figure C.6. Use a pipeline timing chart like that shown in Figure C.8. Assume that the branch is handled by predicting it as taken. If all memory references take 1 cycle, how many cycles does this loop take to execute?
[ 1 5 1 5 ? ? 1 5 1 5 ? ? 2 5 1 0 ? 1 5 ] < A . 2

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