$(15$pt$)$ Consider the following ARM code.

ldr r$0,[$r$1]$

add r$2,$r$0,$r$0$

Our ARM architecture is implemented in $5$ stage pipelining: IF$,$ ID$,$ EX$,$ MEM, WB$.$ Assume that the load instruction requires $4$ cycles at MEM stages. The other stage takes a cycle. Therefore, it takes $10$ cycles to execute two instructions.

$($a$)$ If two threads executing the code are executed in fine grain multithreading, then how many cycles are required to complete the two threads.

$($b$)$ If four threads executing the code are executed in fine grain multithreading, then how many cycles are required to complete the two threads.

$($c$)$ If four threads executing the code are executed in coarse grain multithreading, then how many cycles are required to complete the four threads. Assume there is no L$2-$cache miss for the execution of the code.