1- A 4-bit asynchronous binary counter is shown in Figure 9-8(a). Each D flip-flop is negative...

 

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1- A 4-bit asynchronous binary counter is shown in Figure 9-8(a). Each D flip-flop is negative edge-triggered and has a propagation delay for 10 nanoseconds (ns). Develop a timing diagram showing the Q output of each flip-flop, and determine the total propa- gation delay time from the triggering edge of a clock pulse until a corresponding change can occur in the state of Q3. Also determine the maximum clock frequency at which the counter can be operated. FF0 Do FFI FF2 FF3 Q2 D D2 D3 CLK C Q3 (a) CLK 20 02 23 15|16|_ 1- A 4-bit asynchronous binary counter is shown in Figure 9-8(a). Each D flip-flop is negative edge-triggered and has a propagation delay for 10 nanoseconds (ns). Develop a timing diagram showing the Q output of each flip-flop, and determine the total propa- gation delay time from the triggering edge of a clock pulse until a corresponding change can occur in the state of Q3. Also determine the maximum clock frequency at which the counter can be operated. FF0 Do FFI FF2 FF3 Q2 D D2 D3 CLK C Q3 (a) CLK 20 02 23 15|16|_