1)

a)

b)

c)

d)

This question is about the Verilog code below. module swap4(c,d); input [3:0] c; output [3:0] d; wire [3:0] e, f swap2 swp1 (.a (c[1:0]),b(e[3:2])); swap2 swp2 (.a (c[3:2]),b(e[1:0])); swap2swp3 (.a(\{e[0],e[3]\}), .b(\{f[0],f[3]\})); swap2swp4(.a(f[1:0]),b(d[3:2])); swap2swp5(.a(f[3:2]),b(d[1:0])); endmodule module swap2(a,b); input [1:0] a; output [1:0] b; assignb[1]=a[0]; assign b[0]=a[1]; endmodule Which bit of the output bus d is connected to c[0] ? Which bit of the output bus d is connected to c[1] ? Which bit of the output bus d is connected to c[2] ? Which bit of the output bus d is connected to c[3]