$1$a$.$ Design a $2-$bit full adder using only n$-$input NAND, NOR and NOT gates that returns all outputs with the minimal gate delay. Your adder should have inputs, a$1,$a$0,$b$1,$b$0,$cin and have outputs s$1,$s$0,$cout. Assume all gates have an equal delay.

$1$b$.$ Give the total number of transistors for this adder. NOR gates: $2$ transistors per input NAND gates: $2$ transistors per input NOT gates: $2$ transistors total.

$1$c$.$ Design a $2-$bit full adder using only only n$-$input NAND, NOR and NOT gates that returns all outputs with the minimal number of transistors. Your adder should have inputs, a$1,$a$0,$b$1,$b$0,$cin and have outputs s$1,$s$0,$cout. NOR gates: $2$ transistors per input NAND gates: $2$ transistors per input NOT gates: $2$ transistors total.

$1$d$.$ Give the maximum gate delay for this adder. Assume all gates have an equal delay.