$1.$ A processor has CPI of $1\mathrm{.}5$ if there is no cache miss

l$$ Cache miss rate is $2\%$ for instruction and $5\%$ for data

l$20\%$ of instructions need to access the data memory

l$$ Cache miss penalty is $100$ clock cycles for I$-$cache and D$-$cache

Compute

$(1)$ The CPI if the memory stall $($i$.$e$.,$ the cycles incurred by cache misses$)$ is considered.

$(2)$ The CPI is both instruction cache and data caches are entirely removed $($i$.$e$.,$ all memory accesses are misses$).$

$(3)$ How much slower are these two cases compared with the perfect situation with no cache misses?