1. a. Summarize the differences among simple instruction pipelining, superscalar, and simultaneous multithreading and Multicore organization. Illustrate with diagrams. (4 marks) b. Using Intel Core Duo, Intel Core i7-990X, ARMII MPCore (RISC) Processor and IBM 2196 Processor (Mainframe) discuss Multicore Organization Alternatives. Illustrate with diagrams. (5 marks). c. Give reasons for the choice by designers to move to a multicore organization rather than increase parallelism within a single processor (4 marks). d. Consider the following problem. A designer has a chip available and must decide what fraction of the chip will be devoted to cache memory (L1, L2, L3). The remainder of the chip can be devoted to a single complex superscalar and/or SMT core or multiple somewhat simpler cores. Define the following parameters: n maximum number of cores that can be contained on the chip k-actual number of cores implemented (1 ... k... n, where r = n/k is an integer) perf (r) sequential performance gain by using the resources equivalent to r cores to form a single processor, where perf(1) = 1. ffraction of software that is parallelizable across multiple cores. Thus, if we construct a chip with n cores, we expect each core to provide sequential performance of 1 and for then cores to be able to exploit parallelism up to a degree of n parallel threads. Similarly, if the chip has k cores, then each core should exhibit a performance of perftr) and the chip is able to exploit parallelism up to a degree of k parallel threads. We can modify Amdhal's law to reflect this situation as follows: Speedup 1 XT p ) perf) i. Justify this modification of Amdahl's law. (3 marks) ii. Using Pollack's rule, we set perfer) = r. Let n = 16. We want to plot speedup as a function of r for f-0.5; -0.9;f-0.975; f = 0.99; f = 0.999. What conclusions can you draw? (2 marks) ii. Repeat part() for n = 256 (2 marks)