$1.$ By convention, a cache is named according to the amount of data it contains $($i$.$e$.,$ a $4$ KiB cache can hold $4$ KiB of data$)$; however, caches also require SRAM to store metadata such as tags and valid bits. For this exercise, you will examine how a cache$$s configuration affects the

total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the caches are byte$-$addressable. $4$ Marks

$($a$)$ Given that addresses and words are $32$ bits. How much data can a direct$-$mapped cache

with $64$ blocks and $4-$word blocks hold? How many total bits are required to implement this cache?

$($b$)$ Given that addresses and words are $64$ bits. What is the cache block size $($in words$)$ of a $32$KiB direct$-$mapped cache with $211$ blocks? How many total bits are required to implement

this cache?

$($c$)$ Given that addresses and words are $64$ bits. How many blocks are required for a $64$ KiB cache with $16-$word blocks? How many total bits are required to implement this cache?

How much bigger is this cache than the $32$ KiB cache described in Part $($b$)?($Notice that, by changing the block size, we doubled the amount of data without doubling the total size of the cache.$)$

$($d$)$ Explain why the $64$ KiB cache in $($c$)$ might provide a slower performance than the $32$KiB cache in $($b$)$ despite its larger data size.