By convention, a cache is named according to the amount of data it contains $($i$.$e$.,$ a $4$ KiB cache can hold $4$KiB of data$)$; however, caches also require SRAM to store metadata such as tags and valid bits. For this exercise, you will examine how a cache's configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the caches are byte addressable, and that addresses, and words are $64$ bits. $(5$ Marks$)$

$($a$)$ Calculate the total number of bits required to implement a $32$KiB cache with twoword blocks. $2$ Marks

$($b$)$ Calculate the total number of bits required to implement a $64$KiB cache with $16$word blocks. How much bigger is this cache than the $32$KiB cache described in Part $($a$)?($Notice that, by changing the block size, we doubled the amount of data without doubling the total size of the cache.$)2$ Marks

$($c$)$ Explain why this $64$KiB cache might provide a slower performance than the first cache despite its larger data size. $1$ Mark