1. Consider a Direct Mapped cache with 32-bit memory address reference byte addressable. Assume a 2 word block and a Cache size of 16 Words.

Starting with an empty cache, assume the following memory address references in the corresponding order

Is the underlined reference a hit or a miss in cache?

Select one:

a. MISS

b. HIT

2. Consider a Direct Mapped cache with 32-bit memory address reference byte addressable. Assume a 2 word block and a Cache size of 16 Words.

Starting with an empty cache, assume the following memory address references in the corresponding order

What is the value of the tag bits in cache of the underlined reference above?

Select one:

a. 0

b. 1

c. 2

d. 3

e. 4

3. Consider a Direct Mapped cache with 32-bit memory address reference byte addressable. Assume a 2 word block and a Cache size of 16 Words.

Starting with an empty cache, assume the following memory address references in the corresponding order

What is the final memory address from the above references is located in cache address 4 that is after all references have been passed?

Select one:

a. MEM[32]

b. MEM[96]

c. MEM[88]

d. MEM[256]

e. None of the references

4. Consider an 32-bit Direct Mapped cache with 32-Bytes block and a total cache size of 32768 words, Byte addressable where the word size is 32-bits.

What is the total size in bits for the cache?

Select one:

a. 1114112 bits

b. 1110016 bits

c. 1171456 bits

d. 1048576 bits

e. None of the options

5. Consider an 32-bit Direct Mapped cache with 16-word block and a total cache size of 65536 words, word addressable where the word size is 32-bits.

What is the total size in bits for the cache?

Select one:

a. 2166784 bits

b. 2179072 bits

c. 2097152 bits

d. 2330624 bits

e. 2342912 bits

f. None of the options.

Byte Addresses in Main Memory Address 64 32 92 88 256 128 96 32 96 70 80 90 Byte Addresses in Main Memory Address 64 32 92 88 256 128 96 32 96 70 80 90 Byte Addresses in Main Memory Address 64 32 92 88 256 128 96 32 96