Question 15 Not yet answered Consider a Direct Mapped cache with 32-bit memory address reference byte addressable. Assume a 2 word block and a Cache size of 16 Words. Starting with an empty cache, assume the following memory address references in the corresponding order Marked out of 4.00 P Flag question Byte Addresses in Main Memory Address 64 32 92 88 256 128 96 32 96 What is the final memory address from the above references is located in cache address 3 that is after all references have been passed? Select one: O a. MEM[88] O b. MEM[96] O c. MEM[32] O d. MEM[256] O e. none of the references Question 16 Not yet answered Assume you have a cache with 32K blocks and each block contains 4 words and a 32-bit byte address: What is the total number of tag bits for a 2-way set associative cache? Marked out of 4.00 Select one: O a. 448Kbits Fias question O b. 480Kbits O c. 416Kbits O d. 384Kbits O e none of the options