$1.$ Consider the decade counter shown in Figure $9\mathrm{.}1.$ Let Tint, Tcomp and To$,$ be the propagation delays of the incrementor, comparator and or cell, and Tsetup, Tcq andT,? be the setup time, clock$-$to$-$q delay and reset$-$to$-$q delay of the register. Determine the maximal clock rate of this counter.

$2.$ Revise the design of the $4-$bit LFSR in Section $9\mathrm{.}2\mathrm{.}3$ to include the $"0000"$ pattern but exclude the $"1111"$ pattern.

$3.$ Let the propagation delay of an xor cell be $4$ ns$,$ the propagation delay of an n$-$bit incrementor be $6$n ns$,$ and the setup time and clock$-$to$-$q delay of the register be $2$ and $3$ ns respectively.

$($a$)$ Determine the maximal operation rates of a $4-$bit LFSR and a binary counter.

$($b$)$ Determine the maximal operation rates of an $8-$bit LFSR and a binary counter.

$($c$)$ Determine the maximal operation rates of a $16-$bit LFSR and a binary counter.

$($d$)$ Determine the maximal operation rates of a $64-$bit LFSR and a binary counter.

$4.$ A stuck is a buffer in which the data is stored and retrieved injht$-$in$-$lust$-$out fashion. In a synchronous stack, it should consist of the following I$0$ signals:

w$-$data and r$-$data: data to be written $($also known as pushed$)$ into and read $($also known as popped$)$ from the stack

Push and pop: control signals to enable the push or pop operation.

full and empty: status signals

$0$ clk and reset: the clock and reset signals.

We can use a register file to construct this circuit. by following the design approach of the FIFO buffer.

$($a$)$ Draw a top$-$level diagram similar to that in Figure $9\mathrm{.}13.$

$($b$)$ Consider a stack of four words. Derive the VHDL code of the control circuit.

$5.$ Consider a combinational circuit that requires $128$ ns to process input data and assume that it can always be divided into smaller parts of equal propagation delays. Let Tcp and Tsetvp of the register be $1$ and $3$ ns respectively. Determine the throughput and delay

$($a$)$ of the original circuit.

$($b$)$ if the circuit is converted into a $2-$stage pipeline.

$($c$)$ if the circuit is converted into a $4-$stage pipeline.

$($d$)$ if the circuit is converted into an $8-$stage pipeline.

$($e$)$ if the circuit is converted into a $16-$stage pipeline.

$($f$)$ if the circuit is converted into a $32-$stage pipeline.