$1.$ Counter$-$Based FSMs

You are tasked with designing a sprinkler system controller for a garden that operates in the following cycle: Watering Zone $1($output W$1)$ for $20$ seconds, Watering Zone $2($output W$2)$ for $15$ seconds, Watering Zone $3($output W$3)$ for $10$ seconds, followed by a rest period $($output R$)$ for $5$ seconds before repeating the cycle. The system operates with a clock signal of $5$ seconds per period. This pattern will repeat indefinitely.

A$.$ How many states, N$,$ are needed in a finite state machine $($FSM$)$ to implement this controller? How many states will correspond to watering each of the zones $($Zone $1,$ Zone $2,$ Zone $3),$ and how many will correspond to the rest period? What is the minimum number of state bits, M $,$ required to implement this controller?

B$.$ Draw the state diagram for the FSM that implements this controller. Label the states corresponding to watering Zone $1$ as ZONE$1\backslash (1\_\{1\}\backslash ),$ZONE$1\backslash (\{\}\_\{2\}\backslash ),...,$ and so on for Zone $2$ and Zone $3.$ Label the rest states as REST $\backslash (\_\{1\}\backslash ),$ REST $\backslash (\_\{2\},\backslash$ldots $\backslash )$

C$.$ You are provided with a down$-$counter as a "black$-$box" component with the following properties: $(1)$ It counts down by $1$ on each clock cycle. $(2)$ When the counter reaches $0,$ it loads the next state defined by the bit pattern $\backslash (\backslash$mathrm$\{$L$\}[\backslash$mathrm$\{$M$\}-1],\backslash$mathrm$\{$L$\}[\backslash$mathrm$\{$M$\}-2],\backslash$ldots$,\backslash$mathrm$\{$LO$\}\backslash )$ and continues counting down from there.

You will use this down$-$counter to implement your FSM$.$ Follow these steps: $(1)$ Assign the highest needed binary values to the states corresponding to watering Zone $1,$ the next highest to the states corresponding to Zone $2,$ the next to Zone $3,$ and the lowest binary values to the rest period states. $(2)$ Based on this assignment, create Karnaugh maps for the four outputs: W$1($watering Zone $1),$ W$2($watering Zone $2),$ W$3($watering Zone $3),$ and R$($rest period$).(3)$ Ensure your design accounts for possible undefined states by assigning outputs to guarantee safe behavior in case the counter enters an undefined state. Explain your choice for the output in undefined states. $(4)$ Minimize the Boolean expressions for each output to optimize the area $($use the sum of literals and operators to estimate the area$).(5)$ Sketch a circuit diagram using the down$-$counter as the core component. Ensure you represent it as a rectangular box with the clock input CLK on the bottom, the load inputs $\backslash (\backslash$mathrm$\{$L$\}[\backslash$mathrm$\{$M$\}-1]\backslash )$ to LO on the left, and the counter outputs $\backslash (\backslash$mathrm$\{$Q$\}[\backslash$mathrm$\{$M$\}-1]\backslash )$ to QO on the right.