1) Design a 128KB direct-mapped data cache that uses a 32-bit address and 16 bytes per block. Calculate the following:

a) How many bits are used for the byte offset (without having a separate word offset)?

B) How many bits are used for the index field?

C) How many bits are used for the tag?

(10 points)

2. For a data cache with a 92% hit rate and a 2-cycle hit latency, calculate the average memory access latency (AMAT). Assume that latency to memory and the cache miss penalty together is 124 cycles. Note: The cache must be accessed after memory returns the data. (10 points)