Question: 1 . Design a clock divider based on an asynchronous counter Create a clock divider that uses a structural asynchronous counter built from Xilinx flip

1. Design a clock divider based on an asynchronous counter
Create a clock divider that uses a structural asynchronous counter built from Xilinx flip-flop primitives. The counter uses the main Blackboard 100Mhz clock as an input, and it should generate a clock signal below 1Hz to drive the LED (hint: see the Asynch Divider topic document)

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