1. Design a one-bit ripple carry full adder with Verilog in VIVADO. Take snapshots of the following from your computer screen: 1) The code II) The Schematic ili) The timing diagrams Implement the code in FPGA. 2. Design a 2 to 1 multiplexer. Take snapshots of the following from your computer screen: i) The code ii) The Schematic iii) The timing diagrams Design an 8 to 1 multiplexer using 2 to 1 multiplexer. Take snapshots of the following from your computer screen: i) The code ii) The Schematic iii) The timing diagrams Implement the 8 to 1 mux in FPGA. Your second customer wants to determine the dissipated electrical power by a personal computer, which has a fan that draws 5 L/s of air at 101.325 kPa and 21C through the box containing the CPU and other components. After that air leaves at 101.325 kPa and 30 C. Figure 2: Schematic for task 2. You must follow the following parts to do your task: