1. Draw an ASM chart for the finite state machine. 2. Write an Verilog module to FSM (Named fsm.v) 3. Write a module for counter(Named counter.v) 4. Create a top module named top.v (see figure 1) 5. Simulate the circuit (create testbench module named test.v) done cnten clk reset start count FMS cntcir Counter clk eset 1. Draw an ASM chart for the finite state machine. 2. Write an Verilog module to FSM (Named fsm.v) 3. Write a module for counter(Named counter.v) 4. Create a top module named top.v (see figure 1) 5. Simulate the circuit (create testbench module named test.v) done cnten clk reset start count FMS cntcir Counter clk eset