Question: Draw an ASM chart for the finite state machine. Write an Verilog module to FSM (Named fsm.v ) Write a module for counter(Named counter.v )

Draw an ASM chart for the finite state machine.

Write an Verilog module to FSM (Named fsm.v)

Write a module for counter(Named counter.v)

Create a top module named top.v (see figure 1)

Simulate the circuit (create testbench module named test.v)

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