1) Draw the circuit diagram using basic gates (AND, OR and NOT) for f where f ab b'c Show that a static-1 hazard is possible in this circuit (Hint: you have to select a pair of input that can cause the glitch: try the pair abc: 111 abc: 101 [that is, while a and c remain in 1, b changes from 1 to 0]. Complete the timing diagram below, and show only the gate delays that are relevant to the glitch) to t1 t2 t0 1 1 1 0 1 0 1 t1 1 0 1 0 0 0 0 t2 1 0 1 1 0 1 1 ab Show how this hazard can be avoided. Draw the hazard free circuit for f