$1.$ Explain what is Synthesis and Tool name

$2.$ Inputs and outputs of Synthesis

$3.$ Technology dependent gate vs Technology independent gate

$4.$ Types of information in

a$.$ RTL $($Behavioral Model or Data Flow Model or both$)$

b$.$ SDC $($Clock$,$ Max Transition, Load, Input$/$Output Delay etc.$)$

c$.$ Lib $($Timing Liberty File $$ Functionality, Cell Propagation Delay, Power Info etc.$)$

d$.$ LEF $($Layout Exchange Format $$ Cell Abstract View$)$

$5.$ Steps of Synthesis and brief explanation

a$.$ Generic Synthesis $($syn$\_$gen$)$

b$.$ Mapping $($syn$\_$map$)$

c$.$ Optimization $($syn$\_$opt$)$