$1.$ In order to design the interlocking $"1011"$ array detector in accordance with the "Mealy" model

a$)$ Draw the state diagram.

b$)$ Create the state table for JK Flip$-$Flop elements $.$

c$)$ Create the state table for D Flip$-$Flop elements.

d$)$ Draw the time diagram consisting of clock, input, states and output if $0,1,1,0,0,1,0$ are applied to the X input respectively $.$

e$)$ Implement the sequential circuit using JK Flip$-$Flop elements and a minimum number of logic gates and install it in the Logisim program. Give the simulation results $.$

f$)$ Implement the sequential circuit using D Flip$-$Flop elements and $4$x$1$ Mux and set it up in the Logisim program. Give the simulation results $.$

$($logisim$)$