5- need help with EE / compE question

5. Design a sequence recognizer. In this problem you will be designing a sequential circuit for a sequence recognizer. You will develop a state diagram with one input variable x and one output variable Z. The output is 1 if and only if the last four input bits are oo10 or oo01. Note that sequences may overlap. Sample input 1 o o 1 1 o o o o 1 o o 1 01 1 1 01 o 01 o Sample output: 0 o o o o o o o 0 1 1 o 01 o o o o o 0 o 01 A) 18 pts] Please draw the state diagram. Label each arc with XIZ. Label the initial state with so and other states with si, S2, S3, etc. And then explain the purpose of each state. Use a minimum number of states. Hint: you only need 5 states and you will use Mealy model. Note that the purpose of state so is given below. You're required to write down the purposes of state si, state S2, state S3, and state S4