$1.$ Modify the single$-$cycle RISC$-$V processor to implement each of the following instructions.

auipc

slli

jalr

$$

See the RISC$-$V assembly language summary sheets $($on Canvas, inside cover of textbook$)$ for the definitions of the instructions.

$1.$ List the changes that need to be made to the processor$$s datapath and$/$or controller.

$2.$ Mark$-$up a copy of the RISC$-$V processor diagram to indicate changes to the data path. Using colored lines to indicate changes is a good way to do this. Name any new control signals.

$3.$ Modify the main decoder truth table and the ALU decoder truth table as needed to implement the instructions.

$4.$ Also mark$-$up any changes to the ALU Decoder and Main Decoder Diagrams and ALU as needed.

$5.$Describe any other changes $($if any$)$ that are required.

Note for each instruction assume you are starting with the single$-$cycle processor shown at the end of this document. Do not build on the capabilities you added from the previous instruction.

ALU Decoder Truth table

$\backslash$begin$\{$tabular$\}\{|$c$|$c$|$c$|$c$|$l$|\}$

$\backslash$hline ALUOp & funct$3$ & op $\backslash (\_\{5\}\backslash ),$ funct$7\backslash (\_\{5\}\backslash )$ & Instruction & ALUControl $\backslash (\_\{2$: $0\}\backslash )\backslash \backslash$

$\backslash$hline $00$ & x & x & lw$,$ sw & $000($add$)\backslash \backslash$

$\backslash$hline $01$ & x & x & beq & $001($subtract$)\backslash \backslash$

$\backslash$hline $\backslash$multirow$\{5\}\{*\}\{10\}$ & $000$ & $\backslash (00,01,10\backslash )$ & add & $000($add$)\backslash \backslash$

$\backslash$cline $\{2-5\}$ & $000$ & $11$ & sub & $001($subtract$)\backslash \backslash$

$\backslash$cline $\{2-5\}$ & $010$ & x & slt & $101($set less than$)\backslash \backslash$

$\backslash$cline $\{2-5\}$ & $110$ & x & or & $011($or$)\backslash \backslash$

$\backslash$cline $\{2-5\}$ & $111$ & x & and & $010($and$)\backslash \backslash$

$\backslash$hline

$\backslash$end$\{$tabular$\}$ Single$-$Cycle RISC$-$V Processor Diagram ALU Diagram Main and ALU Decoder Diagrams Main Decoder Truth Table

$\backslash$begin$\{$tabular$\}\{|$c$|$c$|$c$|$c$|$c$|$c$|$c$|$c$|$c$|$c$|\}$

$\backslash$hline op & Instruct. & RegWrite & ImmSrc & ALUSrc & MemWrite & ResultSrc & Branch & ALUOp & Jump $\backslash \backslash$

$\backslash$hline $3$ & lw & $1$ & $00$ & $1$ & $0$ & $10$ & $0$ & $00$ & $0\backslash \backslash$

$\backslash$hline $35$ & sw & $0$ & $01$ & $1$ & $1$ & $\backslash ($ X X $\backslash )$ & $0$ & $00$ & $0\backslash \backslash$

$\backslash$hline $51$ & R$-$type & $1$ & XX & $0$ & $0$ & $00$ & $0$ & $10$ & $0\backslash \backslash$

$\backslash$hline $99$ & beq & $0$ & $10$ & $0$ & $0$ & $\backslash ($ X X $\backslash )$ & $1$ & $01$ & $0\backslash \backslash$

$\backslash$hline $19$ & I$-$type & $1$ & $00$ & $1$ & $0$ & $00$ & $0$ & $10$ & $0\backslash \backslash$

$\backslash$hline $111$ & jal & $1$ & $11$ & X & $0$ & $10$ & $0$ & $\backslash ($ X X $\backslash )$ & $1\backslash \backslash$

$\backslash$hline

$\backslash$end$\{$tabular$\}$